MK2069-04GILFTR【PDF 10/20 页】IC VCXO CLK TRANSLATOR 56-TSSOP

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Sheet目录2098

6页 7页 8页 9页 [10页]11页 12页 13页 14页

MK2069-04

VCXO-BASED UNIVERSAL CLOCK TRANSLATOR

VCXO AND SYNTHESIZER

IDT VCXO-BASED UNIVERSAL CLOCK TRANSLATOR

MK2069-04

REV J 051310

Note 1: This is the recommended crystal operating range. A crystal as low as 8 MHz can be used, although this may

result in increased output phase noise.

Note 2: The VCXO crystal will be pulled to its minimum frequency when there is no input clock (CLR = 1) due to the

attempt of the PLL to lock to 0 Hz.

Note 3: The minimum practical phase detector frequency is 1 kHz. Through proper loop filter design lower input

frequencies may be possible. Input frequencies as low as 400 Hz have been tested.

Note 4: A higher input clock frequency can be used when RPV divider = 8.

Note 5: The output of RCLK is a positive pulse with a duration equal to VCLK high time, or half the VCLK period.

Note 6: Referenced to ICLK, the skews of VCLK, RCLK and TCLK increase together when leakage is present in the

external VCXO PLL loop filter.

Output Rise Time, VCLK and

RCLK

tOR

0.8 to 2.0 V, CL=15 pF

1.5

Output Fall Time, VCLK and

RCLK

tOF

2.0 to 0.8 V, CL=15 pF

1.5

Output Rise Time, TCLK

tOR

0.8 to 2.0 V, CL=15 pF

0.75

Output Fall Time, TCLK

tOF

2.0 to 0.8 V, CL=15 pF

0.75

Skew, ICLK to VCLK (Note 6)

tIV

Rising edges, CL=15 pF

-5

2.5

+10

Skew, ICLK to RCLK (Note 6)

tIV

Rising edges, CL=15 pF

+20

Skew, ICLK to TCLK (Note 6)

tVT

Rising edges, CL=15 pF

-5

1.5

+10

Nominal Output Impedance

ZOUT

Parameter

Symbol

Conditions

Min.

Typ.

Max. Units

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